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Recently computer architects have started to direct their attention onto other techniques
for improving both the processing time and hardware performance.
Shared-Memory
Parallel
(SMP) computing is very popular technique for speeding
up the processing time
[60-62]. Isaac G.
et al
do propose in reference [63] an heterogeneous computing concept
which is a combination of a general purpose CPUs with an accelerator to improve the
execution efficiency. This model is based on shared memory parallel technique.
J. Batlle
et al
proposed in reference [49] a dedicated parallel architecture based on FPGA
and DSP for real-time image processing. This system has been designed to deal with
pipeline procedures and operators. They have broken the image processing algorithm into
three major steps:
preprocessing, intermediate processing and, at the end,
a post-
processing. All low level functions are performed at the preprocessing level. In the
intermediate level of processing we have some algorithms like segmentation,
motion
estimation and features extraction. In the post-processing level we involve statistical
analysis and artificial intelligence [49].
D. Demigny
et al
proposed in reference [64] a high speed reconfigurable FPGA system for
processing images in real-time. They have considered different architectures and models of
processing architectures such as
Multiple Instruction - Single Data
(MISD) and
Single
Instruction - Multiple Data
(SIMD). The SIMD architecture is very interesting for image
processing because we have the same instruction for multiple data streams.
The main
drawbacks of all mentioned architectures are however: a) that there is no homogenous
design that can cover different image processing algorithms, and b) that for any new
design one has to reconfigure the hardware. It may be possible to design a real-time and
robust image processing architecture for a specific task, but it not easy at all to reconfigure
it for different tasks and procedures.
